HARDWARE ARCHITECTURE & SILICON EXPERIMENTATION

Silicon Lab & Architecture Workbench

An interactive hardware verification environment showcasing live cycle-accurate RISC-V pipelining, non-volatile Memristor Compute-in-Memory (CIM) crossbar arithmetic, and Static Timing Analysis (STA) physical design closure.

SIMULATION KERNEL ACTIVE
STATION 01 // COMPUTER ARCHITECTURE

5-Stage RISC-V Microarchitecture Simulator

Cycle-accurate execution across classic IF / ID / EX / MEM / WB stages with interactive Hazard Detection (load-use stall bubble insertion), Data Forwarding (EX-to-EX & MEM-to-EX bypass), and Branch Prediction flushing.

โ–ถ RV32I PIPELINE CONTROLLER
CYCLE: 0 PC: 0x00 CLOCK: 100 MHz
IF FETCH
[ IDLE ]
PC: 0x00
ID DECODE / REG
[ IDLE ]
Read RS1, RS2
EX ALU EXECUTE
[ IDLE ]
Forwarding Muxes
MEM DATA ACCESS
[ IDLE ]
RAM Read/Write
WB WRITEBACK
[ IDLE ]
Commit to RegFile
REGISTER FILE (x0 - x7)
x0 (zero): 0
x1 (ra): 5
x2 (sp): 10
x3 (gp): 0
x4 (tp): 0
x5 (t0): 0
x6 (t1): 0
x7 (t2): 0
MICROARCHITECTURE SPECS
โ€ข ISA: RV32I Base Integer
โ€ข Hazard Unit: Dynamic Stall on LW-use
โ€ข Forwarding: EX-to-EX, MEM-to-EX
โ€ข Branch Penalty: 2 cycles on taken
STATION 02 // COMPUTE-IN-MEMORY (CIM)

4ร—4 Memristor Crossbar Array & NeuroSim Model

Analog in-memory Vector-Matrix Multiplication ($I_j = \sum V_i \cdot G_{ij}$) modeled on 3-bit quantized RRAM conductance states ($G_0 \dots G_7$) with simulated column 5-bit ADCs and energy profiling based on research with Dr. Vahdat.

EDUCATIONAL 4ร—4 DEMO VS. 128ร—128 NEUROSIM RESEARCH CONFIGURATION: 4ร—4 Educational Crossbar: An interactive workbench to demonstrate analog Vector-Matrix Multiplication ($I_j = \sum V_i \cdot G_{ij}$) and 3-bit discrete conductance states ($G_0 \dots G_7$).
128ร—128 NeuroSim Subarray: The research configuration modeled under Dr. Shaghayegh Vahdat for VGG8 on CIFAR-10, utilizing 5-bit column successive-approximation ADCs. All displayed metrics are simulation estimates from the C++ NeuroSim framework, not physical silicon measurements.
RRAM CROSSBAR ARRAY (4 ร— 4)

Toggle row input voltages ($V_{in}$) or click cells to cycle 3-bit conductance ($G_0 \dots G_7$):

V_IN COL 0 COL 1 COL 2 COL 3
I_COL:
0.0 ฮผA
0.0 ฮผA
0.0 ฮผA
0.0 ฮผA
5b ADC: 0 0 0 0
NEUROSIM BENCHMARK METRICS
DYNAMIC ENERGY: 12.8 fJ / MAC
READ LATENCY: 4.2 ns
QUANTIZATION: 3-bit (8 G levels)
ADC CONVERTER: 5-bit Successive Approx.
BENCHMARK NETWORK: VGG8 / CIFAR-10

How It Works: Each crossbar crosspoint contains an analog RRAM cell. Multiplying input voltages by conductance weights occurs simultaneously across all cells in parallel, yielding column currents by Kirchhoff's current law.

STATION 03 // PHYSICAL DESIGN & ASIC FLOW

Static Timing Analysis (STA) & Clock Skew Closure

Interactive register-to-register timing verification modeled on Synopsys Design Compiler and PrimeTime flows. Test how clock frequency, combinational logic delay, and clock skew impact Setup & Hold Timing Slack.

EDUCATIONAL STA SIMULATOR DISCLAIMER: This educational calculator implements standard textbook static timing equations ($T_{arrival} = T_{cq} + T_{comb}$, $T_{required} = T_{clk} - T_{setup} + T_{skew}$, $Slack_{setup} = T_{required} - T_{arrival}$). Real industrial ASIC signoff (e.g. Synopsys PrimeTime or Cadence Tempus) incorporates multi-corner PVT analysis, On-Chip Variation (OCV/AOCV), transition slew degradation, and interconnect cross-talk noise.
CLOCK PERIOD (T_clk): 5.00 ns
CRITICAL PATH (T_cq + T_comb): 2.80 ns
MAX OPERATING FREQ (F_max): 333.3 MHz
LAUNCH-TO-CAPTURE FLIP-FLOP TIMING PATH
FF_LAUNCH T_cq LOGIC CLOUD T_comb (Datapath) FF_CAPTURE T_setup CLOCK TREE (Skew = T_skew)
CLOCK FREQUENCY (F_clk): 200 MHz (5.00 ns)
Period T_clk = 1 / F_clk. Dictates total time budget for register-to-register transfer.
DATAPATH DELAY (T_comb): 2.40 ns
Propagation delay through combinational gates and interconnect wires between flip-flops.
CLOCK-TO-Q DELAY (T_cq): 0.40 ns
Time required for launch flip-flop output Q to stabilize after positive clock edge.
FF SETUP REQUIREMENT (T_setup): 0.30 ns
Minimum duration input data must remain stable BEFORE capture clock edge arrives.
CLOCK SKEW (T_skew): +0.10 ns
Clock arrival offset: positive skew relaxes setup but tightens hold slack.
DATA ARRIVAL: T_cq + T_comb = 2.80 ns
DATA REQUIRED: T_clk - T_setup + T_skew = 4.80 ns
SETUP SLACK: Required - Arrival = +2.00 ns   |   HOLD SLACK: +2.50 ns
TIMING MET (+2.00 ns)