ELECTRICAL ENGINEERING B.Sc. CANDIDATE

Abolfazl Azad

Electrical Engineering B.Sc. Candidate
University of Tehran · RTL Design | Computer Architecture | Hardware Acceleration | RISC-V

RTL DESIGNCOMPUTER ARCHITECTUREHARDWARE ACCELERATIONRISC-VCOMPUTE-IN-MEMORYFPGA & ASIC FLOW
DOWNLOAD CV ↓ EXPLORE RESEARCH PROJECTS → CONTACT ME →
ABOUT

Electrical Engineering B.Sc. candidate at the University of Tehran focused on digital systems, RTL design, and computer architecture.

Electrical Engineering B.Sc. candidate at the University of Tehran focused on digital systems, RTL design, and computer architecture. Project experience includes SystemVerilog-based matrix-multiplication accelerator design and verification, SystemC-based FIR accelerator integration, and open-source RISC-V SoC verification.

Supervised research spans low-power RTL optimization, hardware-aware weight quantization, and NeuroSim-based memristor/CIM characterization. Seeking research experience in energy-efficient digital design, hardware accelerators, RISC-V systems, and AI hardware.

FEATURED RESEARCH

FEATURED RESEARCH PROJECTS

Primary digital hardware engineering investigations across hardware acceleration, open-source processor verification, SystemC co-design, and memristor compute-in-memory. Detailed architecture specifications, RTL implementations, and verification methodologies are documented in dedicated case studies.

OPEN SOURCE

OPEN-SOURCE RISC-V CONTRIBUTIONS

Upstream verification contributions to the community-standard NEORV32 RISC-V processor. Both pull requests have been merged upstream into official releases.

Upstream Attribution: The NEORV32 project is created and maintained by Stephan Nolting. Abolfazl contributed verified test suite improvements, hardware loopbacks, and IEEE-754 compliance fixes as an open-source contributor.
RESEARCH TAXONOMY

RESEARCH EXPERIENCE & STATUS

Supervised research activities at the University of Tehran. Categorized across completed verification milestones, active ongoing experiments, and planned architectural signoff flows.

TECHNICAL SKILLS

EVIDENCE-BASED TECHNICAL PROFICIENCY

Replacing unsupported percentage ratings with concrete technical evidence. Every skill is paired with verified RTL modules, simulation testbenches, open-source pull requests, or physical design runs.

SILICON LAB
INTERACTIVE HARDWARE WORKBENCH

Silicon Lab — Live Architecture & Hardware Simulation

An interactive, in-browser engineering environment featuring cycle-accurate microarchitecture execution, analog crossbar matrix arithmetic, and textbook Static Timing Analysis (STA) closure.

STATION 01 RV32I 5-Stage Pipeline

Cycle-by-cycle execution, EX/MEM forwarding, hazard stalls, and branch flushing.

STATION 02 Memristor CIM Sandbox

4×4 educational crossbar demonstrating analog vector-matrix multiplication & 3-bit conductance mapping.

STATION 03 STA Timing Closure

Interactive setup & hold slack analysis with parameterized datapath delays and clock skew.

LAUNCH INTERACTIVE SILICON LAB 🧪 ↗ Runs live in browser · Zero installation required
DOCUMENTATION

TECHNICAL REPORTS & SPECIFICATIONS

Access real technical case studies, architecture diagrams, RTL verification testbench reports, and official academic curriculum vitae.

PROJECTS
EXPERIENCE
EDUCATION
SELECTED COURSEWORK
CONTACT

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EMAIL abolfazlazad@ut.ac.ir ↗
GITHUB Abolfazl-Azad ↗
LINKEDIN Abolfazl Azad ↗

MORE DETAILS

Curriculum Vitae

Education, experience, projects, skills, and selected technical work.

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